1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same, and particularly to a semiconductor device including vertical MOS transistors of different channel lengths.
Priority is claimed on Japanese Patent Application No. 2007-315747, filed Dec. 6, 2007, the content of which is incorporated herein by reference.
2. Description of the Related Art
As shown in FIG. 2 of US Patent Application Publication No. 2004/0262681 A1, a conventional three-dimensional transistor, i.e., a vertical MOS transistor, includes a silicon pillar to be a channel between source-drain diffusion layers. The channel portion of the silicon pillar is surrounded by a gate insulating film and a gate electrode. The source-drain diffusion layers are formed on the silicon pillar so as to completely cover the channel portion.
In the vertical MOS transistor, an arrangement of vertical MOS transistors of different withstand voltages are not considered.
Japanese Unexamined Patent Application, First Publication No. 2007-134593 discloses a semiconductor device including two vertical transistors Tr1 in addition to a conventional planar MOS transistor Tr2. Each of the vertical transistors Tr1 includes second-conductive-type diffusion layers on the upper and lower portions of an island-type semiconductor layer, and gate electrodes on both sides of the island-type semiconductor layer through a gate insulating film.
However, these two vertical MOS transistors Tr1 have substantially the same structures and the same channel lengths. Therefore, a circuit design of the semiconductor device is restricted in some cases.
Japanese Unexamined Patent Application, First Publication No. H08-116068 discloses a semiconductor device including an n-channel MOSFET and a p-channel MOSFET. A first island-type layered body forming the n-channel MOSFET includes a first n-type silicon semiconductor layer, a second p-type silicon semiconductor layer, and a third n-type silicon semiconductor layer. A second island-type layered body forming the p-channel MOSFET includes the second p-type silicon semiconductor layer, the third n-type silicon semiconductor layer, and a fourth p-type silicon semiconductor layer. The first and the second island layered bodies have different heights. A thermal oxide film is formed over the first and the second island layered bodies. Gate electrodes are formed on both sides of each of the first and the second island layered bodies. The second p-type silicon semiconductor layer and the third n-type silicon semiconductor layer are used as source-and-drain regions and channel regions.
However, multiple semiconductor layers are included in the above structure, complicating manufacturing processes. Further, the thermal oxide film is so thin that insulation (isolation) is not sufficient. As a result, the gate capacitance stored in the second p-type silicon semiconductor layer and the third n-type silicon semiconductor layer increases, making current-voltage characteristics unstable in some cases.
Further, recent semiconductor devices require high density and low power consumption. However, a microscopic wiring or a contact arrangement design for high density and low power consumption cannot be performed in the structures disclosed in the above related arts.